IPI Interface Interrupt Status Register
| PIXEL_IF_FIFO_UNDERFLOW | The FIFO has become empty before the expected number of pixels (calculated from the packet header) could be extracted to the pixel interface. |
| PIXEL_IF_FIFO_OVERFLOW | The FIFO of pixel interface has lost information because some data arrived and FIFO is already full. |
| PIXEL_IF_FRAME_SYNC_ERR | Whenever in Controller timing mode, notifies if a new frame is received but previous has not been completed. |
| PIXEL_IF_FIFO_NEMPTY_FS | Controller timing mode: The FIFO of pixel interface is not empty at the start of a new frame. If this is expected this interrupt should be masked. Camera timing mode: The FIFO of pixel interface is not empty at the start of a new frame. There are some scenarios where synchronization events of new frame can be lost on IPI interface. |
| PIXEL_IF_HLINE_ERR | Horizontal line time error (only available in Controller timing mode). |
| INT_EVENT_FIFO_OVERFLOW | Reporting internal FIFO overflow. |